Hey BillS,
As the current schematics and board files of the Galileo show (Intel Galileo Development Board Documents), the second PCIe port just has floating pins. The first PCIe port is shown in yellow while the unconnected PCIe port #2 is shown in red in the board file below:
I checked all signal layers using Cadence's Free Viewer (http://www.cadence.com/products/pcb/Pages/downloads.aspx) and it appears that these haven't been routed, so that is definitely something I will talk to the Galileo team about for their second iteration.
Thanks for the Minnowboard + "BOB" suggestion. I can certainly see where it'd be useful to prototype with this new shield. However, since I'm using the current Galileo board rev on the market, I'm stuck with plugging the FPGA into the single PCIe port. Do they also have sensor expansion boards? I didn't seem them immediately on their site.
I'm debating a common bus for the sensors vs. connecting each one individually to the FPGA as a point-to-point. A large common bus would certainly simplify things, I'm just worried about bus contention and how that would affect performance, especially if you're trying to use multiple sensors/devices at once (say, streaming video while reading temperature data).
I understand there are a lot of issues with current Arduino shields with Galileo. Case and point, my post about using the UltimateGPS module, which I was converting over from my homebrew project to Galileo (Re: Adafruit Ultimate GPS). Again, I will pass that on to the Galileo folks for the second board iteration, but for now I'd like to keep this shield I'm designing to primarily sensors, IO devices and an FPGA.
I have found a few FPGAs for relatively cheap that do include a PCIe hard IP core (<$100 per unit on Digikey for the Cyclone IV/V). I'm also looking at a DMA backend for PCIe that would be free for testing purposes and fits well within the logic elements of the FPGAs I'm researching. See my post to Alexander below for more on this. I did take a look at the ECP3 and I noticed that the IP I'm researching for the DMA didn't support their device, but that shouldn't stop me from asking them about the IP and what other FPGAs they have in their pipeline. I'll drop them a note.
The Yocto project looks awesome; it's definitely something I could have used when designing with Petalinux on my Xilinx devkit or with linux on the Zedboard. It is a pain to find commonality between devices and it looks like this takes a big step in helping with that.
Thanks!
Matt